The present invention relates to a microprocessor and, more particularly, to a microprocessor designed to perform predetermined processing in accordance with the stored contents of selected one of a plurality of data register banks.
As shown in FIG. 5, a microprocessor of this type includes a plurality of data register banks 11 to 18 arranged in an internal RAM 1, and a bank selecting circuit 2. Each of the data register banks has a plurality of data registers DR. Predetermined data is stored in each data register DR. When a given data register bank is selected, the stored data of the corresponding data registers DR are read out. The bank selecting circuit 2 includes a bank selecting register 21 having bit registers BR arranged in correspondence with the data register banks 11 to 18 and designed to store 1-bit binary data, and a plurality of AND circuits G21, each having two input terminals for respectively receiving an output from a corresponding one of the bit registers BR and a bank switching signal BS. Each of the data register banks 11 to 18 is constituted by a plurality of data registers DR. With this arrangement, when a bank switching command or an interruption is generated, one of the data register banks 11 to 18 is selected in accordance with an output from one of the AND circuits 21 which is based on the stored contents of the bank selecting register 21, i.e., bit data "1", in response to the bank switching signal BS. Data from the respective data registers DR of the selected data register bank are stored in the corresponding output registers OR, of an output register bank 4c, which are respectively arranged in correspondence with the data registers DR of the data register banks 11 to 18, in accordance with a data switching signal DS. The stored data are then supplied to a CPU.
When a new data register bank is selected by the bank switching signal BS, all the stored contents of the respective output registers OR of the output register bank 4c are replaced with the respective data registers DR of the newly selected data register bank. This state is shown in FIGS. 6A and 6B. The data of the previously used data register bank 12, shown in FIG. 6A, are replaced with the data of the newly selected data register bank 14, shown in FIG. 6B.
Switching of the data register banks 11 to 18 is performed by changing the contents of the bank selecting register 21, i.e., changing the bit position of data "1".
In the above-described conventional microprocessor, when the data register banks 11 to 18 are switched from each other, all the stored contents of the output register bank 4c are updated. For this reason, if part of the previously used data of the output register bank 4c is to be used after a switching operation, the contents of the output register bank 4c before the switch operation must be saved in another register or storage area, and part of the saved data must be set in the output register bank 4c again. That is, a copy operation is required. This decreases the overall processing speed.
In addition, since only one output register bank 4 is used, multitask processing is difficult to perform.